october 1987 revised january 1999 cd4027bc dual j-k master/slave flip-flop with set and reset ? 1999 fairchild semiconductor corporation ds005958.prf www.fairchildsemi.com cd4027bc dual j-k master/slave flip-flop with set and reset general description the cd4027bc dual j-k flip-flops are monolithic comple- mentary mos (cmos) integrated circuits constructed with n- and p-channel enhancement mode transistors. each flip-flop has independent j, k, set, reset, and clock inputs and buffered q and q outputs. these flip-flops are edge sensitive to the clock input and change state on the posi- tive-going transition of the clock pulses. set or reset is independent of the clock and is accomplished by a high level on the respective input. all inputs are protected against damage due to static dis- charge by diode clamps to v dd and v ss . features n wide supply voltage range: 3.0v to 15v n high noise immunity: 0.45 v dd (typ.) n low power ttl compatibility: fan out of 2 driving 74l or 1 driving 74ls n low power: 50 nw (typ.) n medium speed operation: 12 mhz (typ.) with 10v supply ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. connection diagram pin assignments for dip and soic top view truth table i = high level o = low level x = don't care = low-to-high = high-to-low note 1: t n - 1 refers to the time interval prior to the positive clock pulse transition note 2: t n refers to the time intervals after the positive clock pulse transition note 3: level change order number package number package description cd4027bcm m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow body CD4027BCN n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide inputs t n - 1 (note 1) outputs t n (note 2) cl (note 3) jksrqq q i xooo i o xooo i i o oxooo o i xiooio i x x o o x (no change) xxxioxi o xxxoixo i xxxiixi i
www.fairchildsemi.com 2 cd4027bc logic diagram
3 www.fairchildsemi.com cd4027bc absolute maximum ratings (note 4) (note 5) recommended operating conditions (note 5) note 4: absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. they are not meant to imply that the devices should be operated at these limits. the table of recom- mended operating conditions and electrical characteristics provides conditions for actual device operation. note 5: v ss = 0v unless otherwise specified. dc electrical characteristics (note 6) note 6: v ss = 0v unless otherwise specified. note 7: i oh and i ol are tested one output at a time. dc supply voltage (v dd ) - 0.5 v dc to + 18 v dc input voltage (v in ) - 0.5v to v dd + 0.5 v dc storage temperature range (t s ) - 65 c to + 150 c power dissipation (p d ) dual-in-line 700 mw small outline 500 mw lead temperature (t l ) (soldering, 10 seconds) 260 c dc supply voltage (v dd ) 3v to 15 v dc input voltage (v in ) 0v to v dd v dc operating temperature range (t a ) - 40 c to + 85 c symbol parameter conditions - 40 c + 25 c + 85 c units min max min typ max min max i dd quiescent device current v dd = 5v, v in = v dd or v ss 4430 m a v dd = 10v, v in = v dd or v ss 8860 m a v dd = 15v, v in = v dd or v ss 16 16 120 m a v ol low level |i o | < 1 m a output voltage v dd = 5v 0.05 0 0.05 0.05 v v dd = 10v 0.05 0 0.05 0.05 v v dd = 15v 0.05 0 0.05 0.05 v v oh high level |i o | < 1 m a output voltage v dd = 5v 4.95 4.95 5 4.95 v v dd = 10v 9.95 9.95 10 9.95 v v dd = 15v 14.95 14.95 15 14.95 v v il low level v dd = 5v, v o = 0.5v or 4.5v 1.5 1.5 1.5 v input voltage v dd = 10v, v o = 1v or 9v 3.0 3.0 3.0 v v dd = 15v, v o = 1.5v or 13.5v 4.0 4.0 4.0 v v ih high level v dd = 5v, v o = 0.5v or 4.5v 3.5 3.5 3.5 v input voltage v dd = 10v, v o = 1v or 9v 7.0 7.0 7.0 v v dd = 15v, v o = 1.5v or 13.5v 11.0 11.0 11.0 v i ol low level output v dd = 5v, v o = 0.4v 0.52 0.44 0.88 0.36 ma current (note 7) v dd = 10v, v o = 0.5v 1.3 1.1 2.25 0.9 ma v dd = 15v, v o = 1.5v 3.6 3.0 8.8 2.4 ma i oh high level output v dd = 5v, v o = 4.6v - 0.52 - 0.44 - 0.88 - 0.36 ma current (note 7) v dd = 10v, v o = 9.5v - 1.3 - 1.1 - 2.25 - 0.9 ma v dd = 15v, v o = 13.5v - 3.6 - 3.0 - 8.8 - 2.4 ma i in input current v dd = 15v, v in = 0v - 0.3 - 10 - 5 - 0.3 - 1.0 m a v dd = 15v, v in = 15v 0.3 10 - 5 0.3 1.0 m a
www.fairchildsemi.com 4 cd4027bc ac electrical characteristics (note 8) t a = 25 c, c l = 50 pf, t rcl = t fcl = 20 ns, unless otherwise specified note 8: ac parameters are guaranteed by dc correlated testing. note 9: c pd determines the no load ac power consumption of any cmos device. for complete explanation, see 74c family characteristics appli cation note, an-90. typical applications ripple binary counters shift registers symbol parameter conditions min typ max units t phl or t plh propagation delay time v dd = 5v 200 400 ns from clock to q or q v dd = 10v 80 160 ns v dd = 15v 65 130 ns t phl or t plh propagation delay time v dd = 5v 170 340 ns from set to q or reset to q v dd = 10v 70 140 ns v dd = 15v 55 110 ns t phl or t plh propagation delay time v dd = 5v 110 220 ns from set to q or v dd = 10v 50 100 ns reset to q v dd = 15v 40 80 ns t s minimum data setup time v dd = 5v 135 270 ns v dd = 10v 55 110 ns v dd = 15v 45 90 ns t thl or t tlh transition time v dd = 5v 100 200 ns v dd = 10v 50 100 ns v dd = 15v 40 80 ns f cl maximum clock frequency v dd = 5v 2.5 5 mhz (toggle mode) v dd = 10v 6.2 12.5 mhz v dd = 15v 7.6 15.5 mhz t rcl or t fcl maximum clock rise v dd = 5v 15 m s and fall time v dd = 10v 10 m s v dd = 15v 5 m s t w minimum clock pulse v dd = 5v 100 200 ns width (t wh = t wl )v dd = 10v 40 80 ns v dd = 15v 32 65 ns t wh minimum set and v dd = 5v 80 160 ns reset pulse width v dd = 10v 30 60 ns v dd = 15v 25 50 ns c in average input capacitance any input 5 7.5 pf c pd power dissipation capacity per flip-flop 35 pf (note 9)
5 www.fairchildsemi.com cd4027bc physical dimensions inches (millimeters) unless otherwise noted 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow body package number m16a
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. cd4027bc dual j-k master/slave flip-flop with set and reset life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide package number n16e
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